For integrated devices, particularly power devices, suitably adapted semiconductor substrates are needed. Power devices, for example vertical power devices, need semiconductor substrates with a minimal thickness to withstand the rated blocking voltage. The minimal thickness may be, for example 60 μm. On the other hand, during processing of the semiconductor substrate, a higher thickness, for example 600 μm, is desired for mechanical stability. Thick substrates, however, have a high electrical and thermal resistance which may affect the electrical performance of the final devices. After integrating the devices, the substrates are therefore thinned to reduce these resistances.
For cost reasons, typically mechanical or chemical etching and polishing processes are employed for reducing the thickness. As these processes exhibit intrinsic thickness variations of the processed substrates, other processes having pre-defined etch or polishing steps are employed to avoid such variations. For example, buried pn-junctions can be used as etch step. Furthermore, change of material properties or different material combinations can also be used either as etch stop or as layer which allows a separation of substrates. Such “separation layers” must withstand the processing conditions during integration of the devices.
Other approaches uses laser light to generate separation regions in a given distances from the substrate surface. Such processes, however, are very cost-intensive.
Another option for manufacturing semiconductor devices is the use of SOI-wafers which provides for a better dielectric insulation to the bulk substrate. Again, a comparably thin semiconductor layer is typically desired for integrating the devices to reduce parasitic capacitances and to insulate the devices from the bulk material. To produce a thin layer, for example 0.2 μm-10 μm, on a SOI-wafer, a thick semiconductor wafer can be bonded to the SOI-wafer. Before bonding, hydrogen ions are implanted into a given depth of the thick semiconductor wafer to generate a separation region. During bonding, or an additional annealing step, the bonded thick semiconductor wafer splits along the separation region so that a comparably thin layer remains attached to the SOI-wafer. This technique is known as “smart-cut” which is, however, very cost-intensive due to the hydrogen implantation.
On the other hand, thin seed-layers may be needed for some processes, for example for subsequent epitaxial growth. In some cases, semiconductor material is grown on a carrier of a different semiconductor material. After epitaxial growth, the grown layer needs to be removed from the carrier without causing damage to the epitaxial layer.
In view of the above, there is a need for improvement.